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preliminary copyright ? intel corporation, 1997 january 1997 order number: 272748-003 80296sa commercial chmos 16-bit microcontroller the 80296sa is a member of intels 16-bit mcs ? 96 microcontroller family. the 80296sa features 6 mbytes of linear address space, a demultiplexed bus, and a chip-select unit. the external bus can dynamically switch between multiplexed and demultiplexed operation. the device has hardware and instructions to support various digital signal processing algorithms. note this datasheet contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. n 50 mhz operation ? n 6 mbytes of linear address space n 512 bytes of register ram n 2 kbytes of code/data ram n register-register architecture n footprint and functionally compatible upgrade for the 8xc196np and 80c196nu n optional phase-locked loop (pll) circuitry with 2x or 4x clock multiplier n 32 i/o port pins n 19 interrupt sources, 14 with programmable priorities n 4 external interrupt pins and nmi pin n 2 flexible 16-bit timer/counters with quadrature counting capability n 3 pulse-width modulator (pwm) outputs with high drive capability n full-duplex serial port with dedicated baud-rate generator ? 40 mhz standard; 50 mhz is speed premium n chip-select unit 6 chip-select pins dynamic demultiplexed/multiplexed address/data bus for each chip select programmable wait states (0C15) for each chip select programmable bus width (8- or 16-bit) for each chip select programmable address range for each chip select n event processor array (epa) with 4 high-speed capture/compare channels n multiply and accumulate executes in 80 ns using the 40-bit hardware accumulator n 880 ns 32/16 unsigned division n 100-pin qfp package n complete system development support n high-speed chmos technology
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preliminary iii contents 80296sa commercial chmos 16-bit microcontroller 1.0 product overview ................................................................................................................ 1 2.0 nomenclature overview...................................................................................................... 2 3.0 pinout .................................................................................................................................. 3 4.0 signals ................................................................................................................................ 6 5.0 address map ..................................................................................................................... 13 6.0 electrical characteristics................................................................................................... 14 6.1 dc characteristics........................................................................................................ 14 6.2 ac characteristics........................................................................................................ 18 6.2.1 relationship of xtal1 to clkout ....................................................................... 18 6.2.2 explanation of ac symbols ................................................................................... 19 6.2.3 ac characteristics multiplexed bus mode ........................................................ 20 6.2.3.1 system bus timings, multiplexed bus ...................................................... 22 6.2.3.2 ready timing, multiplexed bus ............................................................... 23 6.2.4 ac characteristics demultiplexed bus mode ................................................... 24 6.2.4.1 system bus timings, demultiplexed bus .................................................. 26 6.2.4.2 ready timing, demultiplexed bus .......................................................... 27 6.2.4.3 80296sa deferred bus timing mode ........................................................28 6.2.5 hold#, hlda# timings ....................................................................................... 29 6.2.6 ac characteristics serial port, synchronous mode 0 ...................................... 30 6.2.7 external clock drive .............................................................................................. 31 7.0 thermal characteristics .................................................................................................... 33 8.0 80296sa errata................................................................................................................. 33 9.0 datasheet revision history ............................................................................................... 33 figures 1. 80296sa block diagram ......................................................................................................1 2. the 80296sa family nomenclature ....................................................................................2 3. 80296sa 100-pin qfp package ..........................................................................................3 4. i cc versus frequency in reset ........................................................................................... 17 5. effect of clock mode on clkout...................................................................................... 18 6. system bus timings, multiplexed bus mode ..................................................................... 22 7. example ready timings at 50 mhz, multiplexed bus, buscon x = 1 wait state........... 23 8. system bus timings, demultiplexed bus mode................................................................. 26 9. example ready timings at 50 mhz, demultiplexed bus, buscon x = 1 wait state ...... 27 10. deferred bus mode timing diagram.................................................................................. 28 11. hold#, hlda# timing diagram ....................................................................................... 29 12. serial port waveform synchronous mode 0.................................................................. 30 13. external clock drive waveforms........................................................................................ 31 14. ac testing input and output waveforms during 5.0 volt testing ..................................... 32 15. float waveforms during 5.0 volt testing........................................................................... 32
iv preliminary contents tables 1. description of product nomenclature .................................................................................. 2 2. 80296sa 100-pin qfp pin assignment ............................................................................... 4 3. 80296sa 100-pin qfp pin assignment arranged by functional categories ......................5 4. signal descriptions .............................................................................................................. 6 5. 80296sa address map ...................................................................................................... 13 6. dc characteristics over specified operating conditions.................................................. 14 7. ac timing symbol definitions............................................................................................ 19 8. ac characteristics the 80c296sa will meet, multiplexed bus mode ................................ 20 9. ac characteristics the external memory system must meet, multiplexed bus mode ....... 21 10. ac characteristics the 80c296sa will meet, demultiplexed bus mode ........................... 24 11. ac characteristics the external memory system must meet, demultiplexed bus mode ..25 12. hold#, hlda# timings .................................................................................................... 29 13. serial port timing synchronous mode 0 ....................................................................... 30 14. external clock drive........................................................................................................... 31 15. thermal characteristics ..................................................................................................... 33
preliminary 1 80296sa commercial chmos 16-bit microcontroller 1.0 product overview the 80296sa is a member of intels 16-bit mcs ? 96 microcontroller family. the 80296sa features 6 mbytes of linear address space, a demultiplexed bus, and a chip-select unit. the external bus can dynamically switch between multiplexed and demultiplexed operation. the device has hardware and instructions to support various digital signal processing algorithms. figure 1. 80296sa block diagram code/data ram (2 kbytes) port 3 bus control signals a19:16 ad15:0 memory data bus (16) sio baud- rate generator epa timer 1 timer 2 port 1 port 4 pwm port 2 source 2 addr (24) source 2 data (16) bus controller a15:0 source 1 addr (24) source 1 data (16) destination addr (24) destination data (16) a3175-02 aligner chip-select unit peripheral bus interface memory interface unit register file (3-port ram) instruction sequencer queue alu interrupt controller memory data bus (16) memory addr bus (24) memory addr bus (24) peripheral addr bus (8) peripheral data bus (16)
2 preliminary 80296sa commercial chmos 16-bit microcontroller 2.0 nomenclature overview figure 2. the 80296sa family nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. packaging options s qfp programCmemory options 0 without rom process information no mark chmos product family 296sa device speed 40 40 mhz 50 50 mhz program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
preliminary 3 80296sa commercial chmos 16-bit microcontroller 3.0 pinout figure 3. 80296sa 100-pin qfp package v ss a18 / eport.2 a19 / eport.3 wr# / wrl# rd# bhe# / wrh# ale inst ready rpd once pllen2 v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 v ss xtal1 xtal2 v ss p2.7 / clkout v cc p2.6 / hlda# p2.5 / hold# ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc a3155-02 ad0 nc reset# nmi nc a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss pllen1 p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 nc p3.7 / extint3 p1.0 / epa0 v cc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S80296SA view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
4 preliminary 80296sa commercial chmos 16-bit microcontroller table 2. 80296sa 100-pin qfp pin assignment pin name pin name pin name pin name 1 ad0 26 extint2/p3.6 51 hold#/p2.5 76 rd# 2 nc (see note) 27 nc (see note) 52 hlda#/p2.6 77 wr#/wrl# 3 reset# 28 extint3/p3.7 53 v cc 78 eport.3/a19 4 nmi 29 epa0/p1.0 54 clkout/p2.7 79 eport.2/a18 5 nc (see note) 30 v cc 55 v ss 80 v ss 6 a0 31 epa1/p1.1 56 xtal2 81 v cc 7 a1 32 epa2/p1.2 57 xtal1 82 eport.1/a17 8v cc 33 epa3/p1.3 58 v ss 83 eport.0/a16 9v ss 34 t1clk/p1.4 59 a15 84 ad15 10 a2 35 t1dir/p1.5 60 a14 85 ad14 11 a3 36 v cc 61 a13 86 ad13 12 a4 37 t2clk/p1.6 62 a12 87 ad12 13 a5 38 v ss 63 a11 88 ad11 14 a6 39 t2dir/p1.7 64 a10 89 ad10 15 a7 40 pwm0/p4.0 65 a9 90 ad9 16 v cc 41 pwm1/p4.1 66 a8 91 v ss 17 v ss 42 pwm2/p4.2 67 v ss 92 ad8 18 pllen1 43 p4.3 68 v cc 93 v cc 19 cs0#/p3.0 44 v cc 69 pllen2 94 ad7 20 cs1#/p3.1 45 v ss 70 once 95 ad6 21 cs2#/p3.2 46 txd/p2.0 71 rpd 96 ad5 22 cs3#/p3.3 47 rxd/p2.1 72 ready 97 ad4 23 v ss 48 extint0/p2.2 73 inst 98 ad3 24 cs4#/p3.4 49 breq#/p2.3 74 ale 99 ad2 25 cs5#/p3.5 50 extint1/p2.4 75 bhe#/wrh# 100 ad1 note: for compatibility with future products, tie pin 5 to v cc and leave pins 2 and 27 unconnected.
preliminary 5 80296sa commercial chmos 16-bit microcontroller table 3. 80296sa 100-pin qfp pin assignment arranged by functional categories address & data address & data (continued) input/output power & ground name pin name pin name pin name pin a0 6 ad12 87 cs0#/p3.0 19 v cc 8 a1 7 ad13 86 cs1#/p3.1 20 v cc 16 a2 10 ad14 85 cs2#/p3.2 21 v cc 30 a3 11 ad15 84 cs3#/p3.3 22 v cc 36 a4 12 bus control & status cs4#/p3.4 24 v cc 44 a5 13 name pin cs5#/p3.5 25 v cc 53 a6 14 ale 74 epa0/p1.0 29 v cc 68 a7 15 bhe#/wrh# 75 epa1/p1.1 31 v cc 81 a8 66 breq# 49 epa2/p1.2 32 v cc 93 a9 65 hold# 51 epa3/p1.3 33 v ss 9 a10 64 hlda# 52 eport.0 83 v ss 17 a11 63 inst 73 eport.1 82 v ss 23 a12 62 rd# 76 eport.2 79 v ss 38 a13 61 ready 72 eport.3 78 v ss 45 a14 60 wr#/wrl# 77 p2.2 48 v ss 55 a15 59 p2.3 49 v ss 58 a16 83 processor control p2.4 50 v ss 67 a17 82 name pin p2.5 51 v ss 80 a18 79 clkout 54 p2.6 52 v ss 91 a19 78 extint0 48 p2.7 54 ad0 1 extint1 50 p3.6 26 no connection ad1 100 extint2 26 p3.7 28 name pin ad2 99 extint3 28 p4.3 43 nc 2 ad3 98 nmi 4 pwm0/p4.0 40 nc 5 ad4 97 once 70 pwm1/p4.1 41 nc 27 ad5 96 reset# 3 pwm2/p4.2 42 ad6 95 rpd 71 rxd/p2.1 47 ad7 94 xtal1 57 t1clk/p1.4 34 ad8 92 xtal2 56 t1dir/p1.5 35 ad9 90 pllen1 18 t2clk/p1.6 37 ad10 89 pllen2 69 t2dir/p1.7 39 ad11 88 txd/p2.0 46
6 preliminary 80296sa commercial chmos 16-bit microcontroller 4.0 signals table 4. signal descriptions name type description a15:0 i/o system address bus these address pins provide address bits 0C15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. a19:16 i/o address pins 16C19 these address pins provide address bits 16C19 during the entire external memory cycle during both multiplexed and demultiplexed bus modes, supporting extended addressing of the 1-mbyte address space. note: internally, there are 24 address bits; however, only 20 external address pins (a19:0) are implemented. the internal address space is 16 mbytes (000000Cffffffh) and the external address space is 1 mbyte (00000C fffffh). the microcontroller resets to ff2080h. a19:16 share package pins with eport.3:0. ad15:0 i/o address/data lines these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0C15 are presented on the bus and can be latched using ale or adv#. during the data phase, 8- or 16-bit data is transferred. ad7:0 share package pins with p3.7:0. ad15:8 share package pins with p4.7:0. ale o address latch enable this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (a19:16 and ad15:0 for a multiplexed bus; a19:0 for a demultiplexed bus). an external latch can use this signal to demultiplex address bits 0C15 from the address/data bus in multiplexed mode. bhe# o byte high enable ? during 16-bit bus cycles, this active-low output signal is asserted for word and high- byte reads and writes to external memory. bhe# indicates that valid data is being transferred over the upper half of the system data bus. use bhe#, in conjunction with address bit 0 (a0 for a demultiplexed address bus, ad0 for a multiplexed address/data bus), to determine which memory byte is being transferred over the system bus: bhe# ad0 or a0 byte(s) accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only bhe# shares a package pin with wrh#. ? chip configuration register 0 (ccr0) determines whether this pin functions as bhe# or as wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#.
preliminary 7 80296sa commercial chmos 16-bit microcontroller breq# o bus request this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. when the bus-hold protocol is enabled (wsr.7 is set), the p2.3/breq# pin can function only as breq#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus- hold protocol is disabled (wsr.7 is cleared). the microcontroller can assert breq# at the same time as or after it asserts hlda#. once it is asserted, breq# remains asserted until hold# is deasserted. breq# shares a package pin with p2.3. clkout o clock output output of the internal clock generator. the clkout frequency is ? the internal operating frequency (f). clkout has a 50% duty cycle. clkout shares a package pin with p2.7. cs5:0# o chip-select lines 0C5 the active-low output cs x # is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x or chip select x +1 if remapping is enabled. if the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the cs5# values. immediately following reset, cs0# is automatically assigned to the range ff2000C ff20ffh. cs5:0# share package pins with p3.5:0. epa3:0 i/o event processor array (epa) capture/compare channels high-speed input/output signals for the epa capture/compare channels. for high- speed pwm applications, the outputs of two epa channels (either epa0 and epa1 or epa2 and epa3) can be remapped to produce a pwm waveform on a shared output pin. epa3:0 share package pins with p1.3:0. eport.3:0 i/o extended addressing port this is a standard 4-bit, bidirectional port. eport.3:0 share package pins with a19:16. table 4. signal descriptions (continued) name type description
8 preliminary 80296sa commercial chmos 16-bit microcontroller extint3:0 i external interrupts these programmable interrupts are controlled by the extint_con register. this register controls whether the interrupt is edge-triggered or level-sensitive and whether a rising edge/high level or falling edge/low level activates the interrupt. in standby and powerdown modes, asserting the extint x signal causes the device to resume normal operation. the interrupt does not need to be enabled, but the pin must be configured as a special-function input. if the extint x interrupt is enabled, the cpu executes the interrupt service routine. otherwise, the cpu executes the instruction that immediately follows the command that invoked the power-saving mode. in idle mode, asserting any enabled interrupt causes the device to resume normal operation. extint0 shares a package pin with p2.2, extint1 shares a package pin with p2.4, extint2 shares a package pin with p3.6, and extint3 shares a package pin with p3.7. hlda# o bus hold acknowledge this active-low output indicates that the cpu has released the bus as the result of an external device asserting hold#. when the bus-hold protocol is enabled (wsr.7 is set), the p2.6/hlda# pin can function only as hlda#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus- hold protocol is disabled (wsr.7 is cleared). hlda# shares a package pin with p2.6. hold# i bus hold request an external device uses this active-low input signal to request control of the bus. when the bus-hold protocol is enabled (wsr.7 is set), the p2.5/hold# pin can function only as hold#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (wsr.7 is cleared). hold# shares a package pin with p2.5. inst o instruction fetch when high, inst indicates that an instruction is being fetched from external memory. the signal remains high during the entire bus cycle of an external instruction fetch. inst is low for data accesses, including interrupt vector fetches and chip configuration byte reads. inst is low during internal memory fetches. table 4. signal descriptions (continued) name type description
preliminary 9 80296sa commercial chmos 16-bit microcontroller nmi i nonmaskable interrupt in normal operating mode, a rising edge on nmi generates a nonmaskable interrupt. nmi has the highest priority of all interrupts except trap and unimplemented opcode. assert nmi for greater than one state time to guarantee that it is recognized. if nmi is held high during and immediately following reset, the microcontroller will execute the nmi interrupt service routine when code execution begins. to prevent an inadvertent nmi interrupt vector, the first instruction (at f2080h) must clear the nmi pending interrupt bit. andb int_pend1, #7fh. during idle mode, a rising edge on nmi causes the microcontroller to exit idle mode and branch to the interrupt service routine. once i on-circuit emulation holding once high during the rising edge of reset# places the microcontroller into on-circuit emulation (once) mode. this mode puts all pins, except ready, reset#, once, and nmi, into a high-impedance state, thereby isolating the microcontroller from other components in the system. the value of once is latched when the reset# pin goes inactive. while the microcontroller is in once mode, you can debug the system using a clip-on emulator. to exit once mode, reset the microcontroller by pulling the reset# signal low. to prevent inadvertent entry into once mode, connect the once pin to v ss . p1.7:0 i/o port 1 this is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. port 1 shares package pins with the following signals: p1.0/epa0, p1.1/epa1, p1.2/epa2, p1.3/epa3, p1.4/t1clk, p1.5/t1dir, p1.6/t2clk, and p1.7/t2dir. p2.7:0 i/o port 2 this is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. port 2 shares package pins with the following signals: p2.0/txd, p2.1/rxd, p2.2/extint0, p2.3/breq#, p2.4/extint1, p2.5/hold#, p2.6/hlda#, and p2.7/clkout. p3.7:0 i/o port 3 this is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. port 3 shares package pins with the following signals: p3.0/cs0#, p3.1/cs1#, p3.2/cs2#, p3.3/cs3#, p3.4/cs4#, p3.5/cs5#, p3.6/extint2, and p3.7/extint3. p4.3:0 i/o port 4 port 4 is a standard, 4-bit, bidirectional i/o port with high-current drive capability. port 4 shares package pins with the following signals: p4.0/pwm0, p4.1/pwm1, and p4.2/pwm2. p4.3 has a dedicated package pin. table 4. signal descriptions (continued) name type description
10 preliminary 80296sa commercial chmos 16-bit microcontroller pllen2:1 i phase-locked loop 1 and 2 enable these input pins enable the on-chip clock multiplier feature and select either the doubled or the quadrupled clock speed: pllen2 pllen1 mode 0 0 1x mode; pll disabled; f = f xtal 1 0 1 2x mode; pll enabled; f = 2f xtal 1 1 0 reserved ? 1 1 4x mode; pll enabled; f = 4f xtal 1 ? caution: this reserved combination causes the device to enter an unsupported test mode. pwm2:0 o pulse width modulator outputs these are pwm output pins with high-current drive capability. the duty cycle and frequency-pulse-widths are programmable. pwm2:0 share package pins with p4.2:0. rd# o read read-signal output to external memory. rd# is asserted during external memory reads. ready i ready input this active-high input can be used to insert wait states in addition to those programmed in chip configuration byte 0 (ccb0) and the bus control x register (buscon x) . ccb0 is programmed with the minimum number of wait states (0, 5, 10, 15) for an external fetch of ccb1, and buscon x is programmed with the minimum number of wait states (0C15) for all external accesses to the address range assigned to the chip-select x channel. if the programmed number of wait states is greater than zero and ready is low when this programmed number of wait states is reached, additional wait states are added until ready is pulled high. if the programmed number of wait states is equal to zero, hold the ready pin high. programming the number of wait states equal to zero and holding the ready pin low produces unpredictable results. reset# i/o reset a level-sensitive reset input to, and an open-drain system reset output from, the microcontroller. either a falling edge on reset# or an internal reset turns on a pull- down transistor connected to the reset# pin for 16 state times. in the powerdown, standby, and idle modes, asserting reset# causes the microcontroller to reset and return to normal operating mode. if the phase-locked loop (pll) clock circuitry is enabled, you must hold reset# low for at least 2 ms to allow the pll to stabilize before the internal cpu and peripheral clocks are enabled. after a reset, the first instruction fetch is from ff2080h. table 4. signal descriptions (continued) name type description
preliminary 11 80296sa commercial chmos 16-bit microcontroller rpd i return from powerdown timing pin for the return-from-powerdown circuit. if your application uses powerdown mode, connect a capacitor between rpd and v ss if either of the following conditions are true. ? the internal oscillator is the clock source ? the phase-locked loop (pll) circuitry is enabled (see pllen2:1 signal description) the capacitor causes a delay (at least 2 ms) that enables the oscillator and pll circuitry to stabilize before the internal cpu and peripheral clocks are enabled. refer to the special operating modes chapter of the 80296sa microcontroller users manual for details on selecting the capacitor. the capacitor is not required if your application uses powerdown mode and if both of the following conditions are true. ? an external clock input is the clock source ? the phase-locked loop circuitry is disabled if your application does not use powerdown mode, leave this pin unconnected. rxd i/o receive serial data in modes 1, 2, and 3, rxd receives serial port input data. in mode 0, it functions as either an input or an open-drain output for data. rxd shares a package pin with p2.1. t1clk i timer 1 external clock external clock for timer 1. timer 1 increments (or decrements) on both rising and falling edges of t1clk. also used in conjunction with t1dir for quadrature counting mode. and external clock for the serial i/o baud-rate generator input (program selectable). t1clk shares a package pin with p1.4. t2clk i timer 2 external clock external clock for timer 2. timer 2 increments (or decrements) on both rising and falling edges of t2clk. it is also used in conjunction with t2dir for quadrature counting mode. t2clk shares a package pin with p1.6. t1dir i timer 1 external direction external direction (up/down) for timer 1. timer 1 increments when t1dir is high and decrements when it is low. also used in conjunction with t1clk for quadrature counting mode. t1dir shares a package pin with p1.5. t2dir i timer 2 external direction external direction (up/down) for timer 2. timer 2 increments when t2dir is high and decrements when it is low. it is also used in conjunction with t2clk for quadrature counting mode. t2dir shares a package pin with p1.7. table 4. signal descriptions (continued) name type description
12 preliminary 80296sa commercial chmos 16-bit microcontroller txd o transmit serial data in serial i/o modes 1, 2, and 3, txd transmits serial port output data. in mode 0, it is the serial clock output. txd shares a package pin with p2.0. v cc pwr digital supply voltage connect each v cc pin to the digital supply voltage. v ss gnd digital circuit ground these pins supply ground for the digital circuitry. connect each v ss pin to ground through the lowest possible impedance path. wr# o write ? this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. wr# shares a package pin with wrl#. ? chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. wrh# o write high ? during 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. during 8-bit bus cycles, wrh# is asserted for all write operations. wrh# shares a package pin with bhe#. ? chip configuration registrer 0 (ccr0) determines whether this pin functions as bhe# or wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#. wrl# o write low ? during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. during 8-bit bus cycles, wrl# is asserted for all write operations. wrl# shares a package pin with wr#. ? chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. xtal1 i input crystal/resonator or external clock input input to the on-chip oscillator, internal phase-locked loop circuitry, and the internal clock generators. the internal clock generators provide the peripheral clocks, cpu clock, and clkout signal. when using an external clock source instead of the on- chip oscillator, connect the clock input to xtal1. the external clock signal must meet the v ih specification for xtal1. xtal2 o inverted output for the crystal/resonator output of the on-chip oscillator inverter. leave xtal2 floating when the design uses an external clock source instead of the on-chip oscillator. table 4. signal descriptions (continued) name type description
preliminary 13 80296sa commercial chmos 16-bit microcontroller 5.0 address map table 5. 80296sa address map hex address description (note 1, note 2) addressing modes for data accesses ffffff fff800 external device (memory or i/o) in 1-mbyte mode (ccb1.1=0) a copy of internal code ram in 64-kbyte mode (ccb1.1=1) extended fff7ff ff2080 external program memory (note 3) extended ff207f ff2000 external special-purpose memory (ccbs and interrupt vectors) extended ff1fff ff0400 external device (memory or i/o) connected to address/data bus extended ff03ff ff0000 reserved for in-circuit emulators feffff 0f0000 overlaid memory (reserved for future devices); locations x f0000C x f03ffh are reserved for in-circuit emulators 0effff 010000 external device (memory or i/o) connected to address/data bus extended 00ffff 00f800 internal code ram (code or data); can be windowed by wsr1. in 64-kbyte mode, code ram is identically mapped into page ffh. indirect, indexed, extended, windowed direct 00f7ff 00f000 external device (memory or i/o) connected to address/data bus; can be windowed by wsr1 indirect, indexed, extended, windowed direct 00efff 002000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended 001fff 001f00 internal peripheral special-function registers (sfrs); can be windowed by wsr or wsr1 indirect, indexed, extended, windowed direct 001eff 001c00 reserved (future sfr expansion) 001bff 000400 external device (memory or i/o) connected to address/data bus indirect, indexed, extended 0003ff 000200 reserved (future register file expansion) 0001ff 000100 upper register file (general-purpose register ram) can be windowed by wsr or wsr1 indirect, indexed, extended windowed direct 0000ff 00001a lower register file (general-purpose register ram) direct, indirect, indexed, extended 000019 000000 lower register file (stack pointer and cpu sfrs) direct notes: 1. unless otherwise noted, write 0ffh to reserved memory locations and write 0 to reserved sfr bits. 2. the contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. external memory occupies the boot memory partition, ff2080Cff7ffh. after reset, the default chip- select line (cs0#) is active; the first instruction fetch is from ff2080h.
14 preliminary 80296sa commercial chmos 16-bit microcontroller 6.0 electrical characteristics 6.1 dc characteristics absolute maximum ratings* storage temperature ................................... C60c to +150c supply voltage with respect to v ss ............... C0.5 v to +7.0 v power dissipation ........................................................... 1.5 w operating conditions* t a (ambient temperature under bias) ................ 0c to +70c v cc (digital supply voltage) ............................. 4.5 v to 5.5 v f xtal 1 (input frequency for v cc = 4.5 v C 5.5 v) (note 1, 2, 3)........................................ 16 mhz to 50 mhz notes: 1. this device is static and should operate below 1 hz, but has been tested only down to 16 mhz. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. assumes an external clock. the maximum fre- quency for an external crystal oscillator is 25 mhz. notice : this datasheet contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning : stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 6. dc characteristics over specified operating conditions symbol parameter min typical (note 1) max units test conditions i cc v cc supply current 90 150 ma xtal1 = 50 mhz v cc = 5.5 v device in reset i idle idle mode current 45 60 ma xtal1 = 50 mhz v cc = 5.5 v notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 4. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) individual i ol (ma) i oh (ma) p1.7:3, p4 40 40 p1, p2, p3 10 10 p2 40 40 p4 18 10 p1.2:0, p3 40 40 5. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 6. pin capacitance is not tested. this value is based on design simulations.
preliminary 15 80296sa commercial chmos 16-bit microcontroller i pd powerdown mode current 20 50 a v cc = 5.5 v (note 2) i stdby standby mode 8 15 ma v cc = 5.5 v i li input leakage current (standard inputs) 10 a v ss < v in < v cc v il input low voltage (all pins) C0.5 0.8 v v il 1 input low voltage xtal1 C0.5 0.3 v cc v v ih input high voltage 0.2 v cc +1 v cc + 0.5 v v ih 1 input high voltage xtal1 0.7 v cc v cc + 0.5 v v ol output low voltage (output configured as complementary) (note 3, 4) 0.3 0.45 1.5 v v v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v ol 1 output low voltage on p4.3:0 (output configured as comple- mentary) (note 4) 0.45 0.6 v v i ol = 8 ma i ol = 15 ma v ol 2 output low voltage in reset on ale, inst, and nmi 0.45 v i ol = 3 a v ol 3 output low voltage in reset on once pin 0.45 v i ol = 30 a v ol 4 output low voltage on xtal2 0.3 0.45 1.5 v v v i ol = 100 a i ol = 700 a i ol = 3 ma v oh output high voltage (output configured as complementary) (note 4) v cc C 0.5 v cc C 0.9 v cc C 1.5 v v v i oh = C200 a i oh = C3.2 ma i oh = C7.0 ma v oh 1 output high voltage in reset (note 5) v cc C 0.7 v i oh = C3 a table 6. dc characteristics over specified operating conditions (continued) symbol parameter min typical (note 1) max units test conditions notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 4. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) individual i ol (ma) i oh (ma) p1.7:3, p4 40 40 p1, p2, p3 10 10 p2 40 40 p4 18 10 p1.2:0, p3 40 40 5. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 6. pin capacitance is not tested. this value is based on design simulations.
16 preliminary 80296sa commercial chmos 16-bit microcontroller v oh 2 output high voltage on xtal2 v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C100 a i oh = C700 a i oh = C3 ma v oh 3 output high voltage on ready in reset v cc C1.1 v v th + C v th C hysteresis voltage width on reset# pin 0.3 v c s pin capacitance (any pin to v ss ) (note 6) 10 pf r rst reset pull-up resistor 50 150 k w v cc = 5.5 v, v in = 4.0 v table 6. dc characteristics over specified operating conditions (continued) symbol parameter min typical (note 1) max units test conditions notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 4. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) individual i ol (ma) i oh (ma) p1.7:3, p4 40 40 p1, p2, p3 10 10 p2 40 40 p4 18 10 p1.2:0, p3 40 40 5. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 6. pin capacitance is not tested. this value is based on design simulations.
preliminary 17 80296sa commercial chmos 16-bit microcontroller figure 4. i cc versus frequency in reset a4379-01 140 120 100 80 60 40 20 0 5 0 10 15202530 3540 4550 frequency (mhz) i cc (ma)
18 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2 ac characteristics 6.2.1 relationship of xtal1 to clkout figure 5. effect of clock mode on clkout clkout clkout t = 80ns t = 40ns t = 20ns clkout t xhch xtal1 (12.5 mhz) f pllen2:1=01 f pllen2:1=11 f pllen2:1=00 a3160-02
preliminary 19 80296sa commercial chmos 16-bit microcontroller 6.2.2 explanation of ac symbols each ac timing symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. table 7. ac timing symbol definitions character signal(s) a ad15:0, a19:0 bbhe# br breq# cclkout d ad15:0, ad7:0, rxd (sio mode 0 input data) hhold# ha hlda# lale q ad15:0, ad7:0, rxd (sio mode 0 output data) r rd# scs x # w wr#, wrh#,wrl# x xtal1, txd (sio clock) y ready character condition h high l low vvalid x no longer valid z floating (low impedance)
20 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.3 ac characteristics multiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 8. ac characteristics the 80c296sa will meet, multiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 50 (1) mhz frequency on xtal1, pll in 2x mode 8 (2) 25 mhz frequency on xtal1, pll in 4x mode 8 (2) 12.5 mhz f operating frequency, f = f xtal 1 ; pll in 1x mode 16 50 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode operating frequency, f = 4f xtal 1 ; pll in 4x mode t period, t = 1/f 20 62.5 ns t xhch xtal1 rising edge to clkout high or low 3 50 ns t clcl clkout cycle time 2t ns t chcl clkout high period t C 10 t + 15 ns t avwl address valid to wr# falling edge 2t C 25 ns t cllh clkout falling edge to ale rising edge C13 10 ns t llch ale falling edge to clkout rising edge C15 15 ns t lhlh ale cycle time 4t ns (3) t lhll ale high period t C 10 t + 10 ns t avll address valid to ale falling edge t C 15 ns t llax address hold after ale falling edge 1 ns t llrl ale falling edge to rd# falling edge 3 ns t rlcl rd# low to clkout falling edge C10 20 ns t rlrh rd# low period 2t C 25 ns (3) t rhlh rd# rising edge to ale rising edge t C 5 t + 15 ns (4) t rlaz rd# low to address float 5 ns t llwl ale falling edge to wr# falling edge 4 ns t qvwh data stable to wr# rising edge 2t C 27 ns ( 3 ) t chwh clkout high to wr# rising edge C15 5 ns t wlwh wr# low period 2t C 25 ns (3) notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if wait states are used, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles. 5. 8-bit bus only.
preliminary 21 80296sa commercial chmos 16-bit microcontroller t whqx data hold after wr# rising edge t C 7 ns t whlh wr# rising edge to ale rising edge t C 15 t + 20 ns t whbx bhe#, inst hold after wr# rising edge 0 ns t whax ad15:8 hold after wr# rising edge t C 4 ns (5) t rhbx bhe#, inst hold after rd# rising edge 0 ns t rhax ad15:8 hold after rd# rising edge t C 4 ns (5) t w hsh a19:16, cs# hold after wr# rising edge 0 ns t rhsh a19:16, cs# hold after rd# rising edge 0 ns table 9. ac characteristics the external memory system must meet, multiplexed bus mode symbol parameter min max units t avdv ad15:0 valid to input data valid 3t C 32 ns (1, 2) t rldv rd# active to input data valid 2t C 40 ns (1, 2) t sldv chip select low to data valid 4t C 28 ns (1, 2) t chdv clkout high to input data valid 2t C 25 ns t rhdz end of rd# to input data float t C 3 ns (2) t rxdx data hold after rd# inactive 0 ns t avyv ad15:0 valid to ready (inactive) setup 2t C 42 ns (3) t ch 1 yx first ready hold (active) after clkout high t C 4 2t C 21 ns (4, 5) t ch 2 yx non-first ready hold (active) after clkout high 0 2t C 21 ns (4) t ylyh non-ready (inactive) time 2t no upper limit ns notes: 1. if using the ready signal to insert wait states, you must program at least one wait state in the buscon x register because the first falling edge of ready is not synchronized with a clkout edge. 2. if using the buscon x register without the ready signal to insert wait states, add 2t n , where n = number of wait states. 3. if using the buscon x register to insert wait states, add 2t ( n C1), where n = number of wait states. 4. exceeding the maximum specification causes additional wait states. 5. if you program two or more wait states in the buscon x register, the t ch 1 yx minimum does not apply. table 8. ac characteristics the 80c296sa will meet, multiplexed bus mode (continued) symbol parameter min max units notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if wait states are used, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles. 5. 8-bit bus only.
22 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.3.1 system bus timings, multiplexed bus figure 6. system bus timings, multiplexed bus mode clkout ale rd# a3251-01 ad15:0 (read) wr# ad15:0 (write) bhe#, inst ad15:8 (8-bit mode) a19:16 t lhlh address out extended address out t t cllh t clcl t chdv t rlcl t chcl t llch t llrl t rhlh t rlrh t rldv t rhdz data in t rlaz t llax address out t avdv t avll t chwh t whlh t llwl t wlwh t whqx data out address out t wlwh t qvwh t whbx , t rhbx high address out t whsh , t rhsh cs x # t whax , t rhax t lhll
preliminary 23 80296sa commercial chmos 16-bit microcontroller 6.2.3.2 ready timing, multiplexed bus figure 7. example ready timings at 50 mhz, multiplexed bus, buscon x = 1 wait state clkout non-first ready first ready ale a5330-01 t ch 1 yx rd# ad15:0 (read) ad15:0 (write) bhe#,inst a19:16 cs0# t avyv addr out wr# ch2 ch1 ch0 ch3 tt t tt t t ylyh data in addr out data out t ch 2 yx t avdv + 2t t rldv + 2t t wlwh + 2t t qvwh + 2t t rlrh + 2t t lhlh + 2t
24 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.4 ac characteristics demultiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 10. ac characteristics the 80c296sa will meet, demultiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 50 (1) mhz frequency on xtal1, pll in 2x mode 8 (2) 25 mhz frequency on xtal1, pll in 4x mode 8 (2) 12.5 mhz f operating frequency, f = f xtal 1 ; pll in 1x mode 16 50 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode operating frequency, f = 4f xtal 1 ; pll in 4x mode t period, t = 1/f 20 62.5 ns t avwl address valid to wr# falling edge t C 10 ns t avrl address valid to rd# falling edge t C 10 ns t rhrl read high to next read low t C 5 ns t xhch xtal1 high to clkout high or low 3 50 ns t clcl clkout cycle time 2t ns t chcl clkout high period t C 10 t + 15 ns t cllh clkout falling edge to ale rising edge C13 10 ns t llch ale falling edge to clkout rising edge C15 15 ns t lhlh ale cycle time 4t ns (3,4) t lhll ale high period t C 10 t + 10 ns t rlcl rd# low to clkout falling edge C5 11 ns t rlrh rd# low period 3t C 18 ns (3) t rhlh rd# rising edge to ale rising edge t C 4 t + 15 ns ( 4 ) t wlcl wr# low to clkout falling edge C8 9 ns t qvwh data stable to wr# rising edge 3t C 10 ns (4) t chwh clkout high to wr# rising edge C11 10 ns t wlwh wr# low period 3t C 10 ns (3) t whqx data hold after wr# rising edge t C 5 t + 20 ns t whlh wr# rising edge to ale rising edge t C 5 t + 10 ns (3) notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if using either ready or buscon x to insert wait states, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles.
preliminary 25 80296sa commercial chmos 16-bit microcontroller t whbx bhe#, inst hold after wr# rising edge 0 ns t whax a19:0, cs x # hold after wr# rising edge 0 ns t rhbx bhe#, inst hold after rd# rising edge 0 ns t rhax a19:0, cs x # hold after rd# rising edge 0 ns table 11. ac characteristics the external memory system must meet, demultiplexed bus mode symbol parameter min max units t avdv a19:0 valid to input data valid 4t C 28 ns (1, 2, 3) t rldv rd# active to input data valid 3t C 25 ns (1, 2) t sldv chip select low to data valid 4t C 28 ns (1, 2, 3) t chdv clkout high to input data valid 2t C 25 ns t rhdz end of rd# to input data float t ns (2, 3) t rxdx data hold after rd# inactive 0 ns t avyv a19:0 valid to ready setup 3t C 45 ns (4) t ch 1 yx first ready hold (active) after clkout high t C 4 2t C 21 ns (5, 6) t ch 2 yx non-first ready hold (active) after clkout high 0 2t C 21 ns (5) t ylyh non ready (inactive) time 2t no upper limit ns notes: 1. if using the ready signal to insert wait states, you must program at least one wait state in the buscon x register because the first falling edge of ready is not synchronized with a clkout edge. 2. if using the buscon x register without the ready signal to insert wait states, add 2t n , where n = number of wait states. 3. if cs x # changes or if a write cycle follows a read cycle, add 2t (1 state). 4. if using the buscon x register to insert wait states, add (2t n C1), where n = number of wait states. 5. exceeding the maximum specification causes additional wait states. 6. if you program two or more wait states in the buscon x register, the t ch 1 yx minimum does not apply. table 10. ac characteristics the 80c296sa will meet, demultiplexed bus mode (continued) symbol parameter min max units notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if using either ready or buscon x to insert wait states, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles.
26 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.4.1 system bus timings, demultiplexed bus figure 8. system bus timings, demultiplexed bus mode clkout ale rd# a3253-02 ad15:0 (read) wr# ad15:0 (write) bhe#, inst a19:0 address out t chcl t clcl t llch t chwh t lhlh t whlh t rhrl t rhdz data in t rlrh t avdv t whqx t whax t wlcl data out t wlwh t qvwh t whbx , t rhbx cs x # t lhll t cllh t t rhlh t avrl t rhax t sldv t chdv t rldv t avwl
preliminary 27 80296sa commercial chmos 16-bit microcontroller 6.2.4.2 ready timing, demultiplexed bus figure 9. example ready timings at 50 mhz, demultiplexed bus, buscon x = 1 wait state t avyv clkout non-first ready first ready ale a3258-02 t ch 1 yx t avdv + 2t rd# ad15:0 (read) ad15:0 (write) bhe#,inst a19:0 cs x # t rlrh + 2t t avyv data out address out data in t rldv + 2t t wlwh + 2t t qvwh + 2t wr# ch2 ch1 ch0 ch3 tt tt t t t lhlh + 2t t ylyh t ch 2 yx
28 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.4.3 80296sa deferred bus timing mode the deferred bus cycle mode is desi gned to reduce bus contention when using the 80296sa in demultiplexed mode with slow memory devices. unlike the 8xc196nu, in which this bus mode has to be enabled through the ccr to take advantage of the feature, the 80296sa automatically invokes this mode whenever the appropriate conditions occur. in the deferred mode, a delay of the wr# signal and the next bus cycle will occur in the first bus cycle following a chip-select change and in the first write cycle following a read cycle. this mode will work in parallel with wait states. refer to figure 11 to determine which control signals are affected. cycle 1 is a normal 4t read cycle. cycle 2 is a write cycle that follows a read cycle, so a 2t delay of the next bus cycle is inserted. notice that the chip-select change at the beginning of cycle 2 did not cause a double delay (4t). the chip-select change in cycle 3, a read cycle, causes a 2t delay. figure 10. deferred bus mode timing diagram clkout ale rd# a3247-02 t whlh + 2t t rhlh + 2t t avrl + 2t t avwl + 2t ad15:0 (read) wr# ad15:0 (write) bhe#, inst a19:0 cs x # t avdv + 2t t lhlh + 2t data in data in data out valid valid data out address out data out
preliminary 29 80296sa commercial chmos 16-bit microcontroller 6.2.5 hold#, hlda# timings figure 11. hold#, hlda# timing diagram table 12. hold#, hlda# timings symbol parameter min max units t hvch hold# setup time (to guarantee recognition at next clock) 30 ns t clhal clkout low to hlda# low C15 15 ns t clbrl clkout low to breq# low C15 15 ns t halaz hlda# low to address float 33 ns t halbz hlda# low to bhe#, inst, rd#, wr# weakly driven 25 ns t clhah clkout low to hlda# high C25 15 ns t clbrh clkout low to breq# high C25 25 ns t hahax hlda# high to address no longer float C20 ns t hahbv hlda# high to bhe#, inst, rd#, wr# valid C20 ns a2460-03 clkout hold# hlda# breq# a19:0, ad15:0 cs x #, bhe#, inst, rd#, wr# wrl#, wrh# ale t cllh t clhah t clbrh t hahax t hahbv t halbz t halaz t clbrl t clhal t hvch t hvch hold latency start of strongly driven ale weakly held inactive
30 preliminary 80296sa commercial chmos 16-bit microcontroller 6.2.6 ac characteristics serial port, synchronous mode 0 figure 12. serial port waveform synchronous mode 0 table 13. serial port timing synchronous mode 0 symbol parameter min max units t xlxl serial port clock period ? sp_baud 3 x 002h sp_baud = x 001h 6t 4t ns ns t xlxh serial port clock falling edge to rising edge ? sp_baud 3 x 002h sp_baud = x 001h 4t C 15 2t C 15 4t + 15 2t + 15 ns ns t qvxh output data setup to clock high (see note) sp_baud 3 x 002h sp_baud = x 001h 4t C 15 2t C 15 4t + 15 2t + 15 ns t xhqx output data hold after clock high 2t C 20 ns t xhqv next output data valid after clock high 2t + 20 ns t dvxh input data setup to clock high (see note) sp_baud 3 x 002h sp_baud = x 001h 2t + 10 t + 10 ns t xhdx input data hold after clock high 0 ns t xhqz last clock high to output float 2t + 15 ns ? the minimum baud-rate (sp_baud) register value is x002h for receptions and x001h for transmissions. valid valid valid valid valid valid valid valid rxd (in) (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh a2080-02 rxd
preliminary 31 80296sa commercial chmos 16-bit microcontroller 6.2.7 external clock drive figure 13. external clock drive waveforms table 14. external clock drive symbol parameter min max units f xtal 1 external input frequency (1/ t xlxl ), pll disabled 16 50 ? mhz external input frequency (1/ t xlxl ), pll in 2x mode 8 25 mhz external input frequency (1/ t xlxl ), pll in 4x mode 8 12.5 mhz t xtal 1 oscillator period (t xlxl ), pll disabled 20 62.5 ns oscillator period (t xlxl ), pll in 2x mode 40 125 ns oscillator period (t xlxl ), pll in 4x mode 80 125 ns t xhxx high time 0.35t xtal 1 0.65t xtal 1 ns t xlxx low time 0.35t xtal 1 0.65t xtal 1 ns t xlxh rise time 10 ns t xhxl fall time 10 ns ? assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 mhz. t xlxx a2119-03 t xhxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v xtal1
32 preliminary 80296sa commercial chmos 16-bit microcontroller figure 14. ac testing input and output waveforms during 5.0 volt testing figure 15. float waveforms during 5.0 volt testing test points 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and 0.8 v for a logic 0. 3.5 v 0.45 v a2120-04 2.0 v 0.8 v v load v load C 0.15 v v load + 0.15 v timing reference points v oh C 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2121-03
preliminary 33 80296sa commercial chmos 16-bit microcontroller 7.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values will change depending on operating conditions and the application. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 8.0 80296sa errata the 80296sa may contain design defects or errors known as errata. characterized errata that may cause the 80296sas behavior to deviate from published specifications are documented in a specification update. specification updates can be obtained from your local intel sales office or from the world wide web ( www.intel.com ). 9.0 datasheet revision history this datasheet is valid for devices with an a at the end of the topside tracking number. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this is the -003 version of the datasheet. the following changes were made in this version: 1. all references to sqfp package were deleted. 2. reference to rom option was removed from table 1. 3. the speed designation for 40 mhz was changed from no mark to 40 in table 1. 4. the t rxdx specification was changed to 0 ns (from 2 ns) in table 11 and table 13. 5. the t chyx specification was replaced by t ch 1 yx and t ch 2 yx . 6. the ready timing diagrams (figures 8 and 10) were replaced by examples that reflect the new t ch 1 yx and t ch 2 yx specifications. this is the -002 version of the datasheet. the following changes were made in this version: 1. the intel confidential designation was removed for publication. 2. a heading was added for section 1.0, product overview, and the remaining sections were renum- bered. 3. the errata list was replaced with a reference to the specification update document. the following changes were made in the -001 version of the datasheet: 1. throughout the datasheet, the product name was changed to read 80296sa instead of 80c296sa. 2. the feature list was clarified. 3. a table of contents was added. 4. the block diagram was changed. 5. several sections were rearranged and section numbers were assigned. thermal characteristics was moved to section 7.0; a section heading was added for nomenclature overview, section 2.0; a section heading was added for address map and it was moved to section 5.0; a section heading was added for pinout, and it was moved to section 3.0; the section heading pin descriptions was changed to signals, section 4.0. the remaining sections were assigned section numbers: electrical characteris- table 15. thermal characteristics package type q ja q jc 100-pin qfp 50 c/w 16 c/w
34 preliminary 80296sa commercial chmos 16-bit microcontroller tics is section 6.0; errata is section 8.0, and datasheet revision history is section 9.0. 6. table 2 was changed to table 1 and the process information was corrected to show that no mark sig- nifies a chmos process. 7. table 3 was changed to table 7 and several clarifications were made. 8. figure 3 was changed to correct the product name. pin assignments did not change. 9. table 4 was changed to table 2 and pin 3 was changed from no connection to tie to v cc . 10. figure 4 was changed to correct the product name. pin assignments did not change. 11. figure 5, i cc versus frequency in reset, was added. remaining figure numbers were incremented. 12. table 6 was changed to table 4 and a note for handling the no connection pins was added. 13. table 8 was changed to table 6. the descriptions of breq#, hlda#, and hold# were changed to reflect their operation during hold. the description of the once signal was changed to reflect the correct states of ready, reset#, and nmi during once mode. the description of pllen2:1 was changed to show the correct pin states to achieve each phase-locked loop (pll) clock multiplier mode. the descrip- tions of rpd and reset# were changed to reflect system requirements w hen using the pll. 14. two notes were added to clarify the operating conditions in the electrical characteristics section. 15. table 9 was changed to table 8, the notes were re-ordered, and the following specifications were changed: ?i cc max was changed to 150 ma (from 120 ma). ?v oh min was changed to v cc C0.5 v (from v cc C0.3 v) at i oh = C200a. ?v oh min was changed to v cc C0.9 v (from v cc C0.7v) at i oh = C3.2 ma. ? test condition for v ol 1 max = 0.45 v was changed to i ol = 8 ma (from i ol = 10 ma). ?r rst min and max were changed to 50 k w and 150 k w (from 9 k w and 95 k w ). ?v oh 3 min specification was added. 16. table 10 was divided into two tables: timing specifications that the microcontroller will meet (table 10) and those that the external memory system must meet (table 11). note 7 was deleted and the remain- ing notes were re-ordered. the following specifications were changed or added in table 10: ?f xtal 1 min for the pll in 4x mode was changed to 8 mhz (from 4 mhz); a clarifying note was added. ?t xhch min was changed to 3 ns (from tbd). ?t llax min was changed to 1 ns (from tbd). ?t llrl min was changed to 3 ns (from tbd) ?t rhax min was changed to t C 4 ns (from t). ?t avwl min (2t C 25) was added to table 10. ?t sldv min (4t C 28) was added to table 11. 17. table 11 was divided into two tables: timing specifications that the microcontroller will meet (table 12) and those that the external memory system must meet (table 13). note 7 was deleted and the remain- ing notes were re-ordered. the following specifications were changed: ?f xtal 1 min for the pll in 4x mode was changed to 8 mhz (from 4 mhz); a clarifying note was added. ?t whqx min was changed to t C 5 ns (from t C 2 ns). 18. figure 6 was changed to show the correct pllen2:1 values to select the 2x clock multiplier mode. 19. table 13 was changed to table 15 and a note was added. 20. table 14 was changed to table 16, 1/t xlxl specifications for each phase-locked loop (pll) mode were added, and note 2 was deleted.
preliminary 35 80296sa commercial chmos 16-bit microcontroller
36 preliminary 80296sa commercial chmos 16-bit microcontroller

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